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Integrated Circuit Systems, Inc.
ICS9DB108
Eight Output Differential Buffer for PCI-Express
Recommended Application: DB800 Intel Yellow Cover part with PCI-Express support. Output Features: * 8 - 0.7V current-mode differential output pairs * Supports zero delay buffer mode and fanout mode * Bandwidth programming available Key Specifications: * Outputs cycle-cycle jitter < 50ps * Outputs skew: 50ps * +/- 300ppm frequency accuracy on output clocks Features/Benefits: * Supports tight ppm accuracy clocks for Serial-ATA * Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread * Supports undriven differential output pair in PD# and SRC_STOP# for power management. Pin Configuration
SRC_DIV# VDD GND SRC_IN SRC_IN# OE_0 OE_3 DIF_0 DIF_0# GND VDD DIF_1 DIF_1# OE_1 OE_2 DIF_2 DIF_2# GND VDD DIF_3 DIF_3# BYPASS#/PLL SCLK SDATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDA GNDA IREF LOCK OE_7 OE_4 DIF_7 DIF_7# GND VDD DIF_6 DIF_6# OE_6 OE_5 DIF_5 DIF_5# GND VDD DIF_4 DIF_4# HIGH_BW# SRC_STOP# PD# GND
48-pin SSOP & TSSOP
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ICS9DB108
Integrated Circuit Systems, Inc.
ICS9DB108
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN NAME SRC_DIV# VDD GND SRC_IN SRC_IN# OE_0 OE_3 DIF_0 DIF_0# GND VDD DIF_1 DIF_1# OE_1 OE_2 DIF_2 DIF_2# GND VDD DIF_3 DIF_3# BYPASS#/PLL SCLK SDATA PIN TYPE IN PWR PWR IN IN IN IN OUT OUT PWR PWR OUT OUT IN IN OUT OUT PWR PWR OUT OUT IN IN I/O DESCRIPTION Active low Input for determining SRC output frequency SRC or SRC/2. 0 = SRC/2, 1= SRC Power supply, nominal 3.3V Ground pin. 0.7 V Differential SRC TRUE input 0.7 V Differential SRC COMPLEMENTARY input Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential true clock outputs 0.7V differential complement clock outputs Ground pin. Power supply, nominal 3.3V 0.7V differential true clock outputs 0.7V differential complement clock outputs Input to select Bypass(fan-out) or PLL (ZDB) mode 0 = Bypass mode, 1= PLL mode Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant.
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Integrated Circuit Systems, Inc.
ICS9DB108
Pin Description (Continued)
PIN # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 PIN NAME GND PD# SRC_STOP# HIGH_BW# DIF_4# DIF_4 VDD GND DIF_5# DIF_5 OE_5 OE_6 DIF_6# DIF_6 VDD GND DIF_7# DIF_7 OE_4 OE_7 LOCK PIN TYPE PWR IN IN PWR OUT OUT PWR PWR OUT OUT IN IN OUT OUT PWR PWR OUT OUT IN IN OUT DESCRIPTION Ground pin. Asynchronous active low input pin used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped. Active low input to stop diff outputs. 3.3V input for selecting PLL Band Width 0 = High, 1= Low 0.7V differential complement clock outputs 0.7V differential true clock outputs Power supply, nominal 3.3V Ground pin. 0.7V differential complement clock outputs 0.7V differential true clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 0.7V differential complement clock outputs 0.7V differential true clock outputs Power supply, nominal 3.3V Ground pin. 0.7V differential complement clock outputs 0.7V differential true clock outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs Active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 3.3V output indicating PLL Lock Status. This pin goes high when lock is achieved. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core.
46 47 48
IREF GNDA VDDA
IN PWR PWR
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Integrated Circuit Systems, Inc.
ICS9DB108
General Description
ICS9DB108 follows the Intel DB400 Differential Buffer Specification. This buffer provides four SRC clocks for PCI-Express, next generation I/O devices. ICS9DB108 is driven by a differential input pair from a CK409/CK410 main clock generator, such as the ICS952601 or ICS954101. ICS9DB108 can run at speeds up to 200MHz. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew (50ps) requirements.
Block Diagram
8 OE(7:0)
SRC_IN SRC_IN#
SPREAD COMPATIBLE PLL
STOP LOGIC
8 DIF(7:0)
SRC_DIV# HIGH_BW# SRC_STOP# PD# BYPASS#/PLL SDATA SCLK CONTROL LOGIC
IREF
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Integrated Circuit Systems, Inc.
ICS9DB108
Absolute Max
Symbol VDD_A VDD_In VIL VIH Ts Tambient Tcase ESD prot Parameter 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Low Voltage Input High Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min Max 4.6 4.6 VDD+0.5V 150 70 115 Units V V V V C C C V
GND-0.5 -65 0
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 Operating Supply Current Powerdown Current Input Frequency3 Pin Inductance
1
CONDITIONS MIN 3.3 V +/-5% 2 GND - 0.3 3.3 V +/-5% VIN = VDD -5 VIN = 0 V; Inputs with no pull-up -5 resistors VIN = 0 V; Inputs with pull-up -200 resistors Full Active, CL = Full load; all diff pairs driven all differential pairs tri-stated VDD = 3.3 V 80
TYP
MAX UNITS NOTES VDD + 0.3 V 0.8 V 5 uA uA uA 250 60 12 mA mA mA MHz nH pF pF MHz MHz 1 33 10 300 5 5 ms kHz ns us ns ns 3 1 1 1 1 1 1,2 1 1,3 1,3 1 2
IDD3.3OP IDD3.3PD Fi Lpin CIN COUT
100/133 166/200
220 7 5 6
Logic Inputs 1.5 Input Capacitance1 Output pin capacitance PLL Bandwidth when PLL_BW=0 PLL Bandwidth BW PLL Bandwidth when PLL_BW=1 From VDD Power-Up and after 1,2 TSTAB input clock stabilization or deClk Stabilization assertion of PD# to 1st clock Triangular Modulation 30 Modulation Frequency DIF output enable after Tdrive_SRC_STOP# SRC_Stop# de-assertion DIF output enable after Tdrive_PD# PD# de-assertion Fall time of PD# and Tfall SRC_STOP# Rise time of PD# and Trise SRC_STOP# 1 Guaranteed by design and characterization, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Time from deassertion until outputs are >200 mV
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Integrated Circuit Systems, Inc.
ICS9DB108
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo
1
CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V
MIN 3000 660 -150 -300 250
TYP
MAX
UNITS
NOTES 1 1,3
VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm
850 mV 150 1150 550 140 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps
1,3 1 1 1 1 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 1
Average period
Tperiod
Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle
Tabsmin tr tf d-tr d-tf dt3
4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175
0 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533
700 700 125 125
Measurement from differential 45 55 % wavefrom VT = 50% tsk3 50 ps Skew PLL mode, 50 ps Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom BYPASS mode as additive jitter 50 ps 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock complies with CK409/CK410 accuracy requirements 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
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Integrated Circuit Systems, Inc.
ICS9DB108
General SMBus serial interface information for the ICS9DB108 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address DC (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address DD (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controlle r (Host) starT bit T Slave Address DC(H ) W Rite WR Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve /Re ce ive r)
Index Block Read Operation
Controlle r (Host) T starT bit Slave Address DC(H ) WR W Rite Beginning Byte = N ACK RT Repeat starT Slave Address DD(H ) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Sla ve /Re ce ive r)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
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Integrated Circuit Systems, Inc.
ICS9DB108
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD) Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Type 0 1 PWD 0 0 X X X 1 1 1
PD# drive mode SRC_Stop# drive mode Reserved Reserved Reserved PLL_BW# adjust BYPASS#/PLL SRC_DIV#
RW driven Hi-Z RW driven Hi-Z Reserved RW Reserved RW Reserved RW RW High BW Low BW RW fan-out ZDB RW x/2 1x
SMBus Table: Output Control Register Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 42,41 38,37 34,33 30,29 20,21 16,17 12,13 8,9 Name DIF_7 DIF_6 DIF_5 DIF_4 DIF_3 DIF_2 DIF_1 DIF_0 Control Function Type Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1
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Integrated Circuit Systems, Inc.
ICS9DB108
SMBus Table: Output Control Register Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 42,41 38,37 34,33 30,29 20,21 16,17 12,13 8,9 Name DIF_7 DIF_6 DIF_5 DIF_4 DIF_3 DIF_2 DIF_1 DIF_0 Control Function Type Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control RW 0 1 Reserved PWD 0 0 0 0 0 0 0 0
RW Free-run Stoppable RW Free-run Stoppable RW RW Reserved Reserved
RW Free-run Stoppable RW Free-run Stoppable RW Reserved
SMBus Table: Output Control Register Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Type Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RW RW RW RW RW RW RW RW 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD X X X X X X X X
SMBus Table: Vendor & Revision ID Register Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function Type R R R R R R R R 0 1 PWD 0 0 0 1 0 0 0 1
REVISION ID
VENDOR ID
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Integrated Circuit Systems, Inc.
ICS9DB108
SMBus Table: DEVICE ID Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Type RW RW RW RW RW RW RW RW 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD 0 0 0 0 1 0 0 0
Device ID 7 (MSB) Device ID 6 Device ID 5 Device ID 4 Device ID 3 Device ID 2 Device ID 1 Device ID 0
SMBus Table: Byte Count Register Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Type 0 1 PWD 0 0 0 0 0 1 0 1
RW RW Writing to this RW register configures RW how many bytes RW will be read back. RW RW RW
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Integrated Circuit Systems, Inc.
ICS9DB108
PD#, Power Down
The PD# pin cleanly shuts off all clocks and places the device into a power saving mode. PD# must be asserted before shutting off the input clock or power to insure an orderly shutdown. PD is asynchronous active-low input for both powering down the device and powering up the device. When PD# is asserted, all clocks will be driven high, or tri-stated (depending on the PD# drive mode and Output control bits) before the PLL is shut down.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of DIF#, all DIF outputs must be held High, or tri-stated (depending on the PD# drive mode and Output control bits) on the next High-Low transition of the DIF# outputs. When the PD# drive mode bit is set to `0', all clock outputs will be held with DIF driven High with 2 x IREF and DIF# tri-stated. If the PD# drive mode bit is set to `1', both DIF and DIF# are tri-stated.
PWRDWN# DIF DIF#
PD# De-assertion
Power-up latency is less than 1 ms. This is the time from de-assertion of the PD# pin, or VDD reaching 3.3V, or the time from valid SRC_IN clocks until the time that stable clocks are output from the device (PLL Locked). If the PD# drive mode bit is set to `1', all the DIF outputs must driven to a voltage of >200 mV within 300 ms of PD# de-assertion.
Tstable <1mS PWRDWN#
DIF DIF# Tdrive_PwrDwn# <300uS, >200mV
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Integrated Circuit Systems, Inc.
ICS9DB108
SRC_STOP#
The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
SRC_STOP# - Assertion
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output to stop). When the SRC_STOP# drive bit is `0', the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the SRC_STOP# drive bit is `1', the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
SRC_STOP# - De-assertion (transition from '0' to '1')
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is 2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is `1' (tri-state), all stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
1mS
SRC_Stop# PWRDWN#
DIF (Free Running) DIF# (Free Running)
DIF (Stoppable) DIF# (Stoppable)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
1mS
SRC_Stop# PWRDWN#
DIF (Free Running) DIF# (Free Running)
DIF (Stoppable) DIF# (Stoppable)
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Integrated Circuit Systems, Inc.
ICS9DB108
SRC_STOP_3 (SRC_Stop = Driven, PD = Tristate)
1mS
SRC_Stop# PWRDWN#
DIF (Free Running) DIF# (Free Running)
DIF (Stoppable) DIF# (Stoppable)
SRC_STOP_4 (SRC_Stop = Tristate, PD = Tristate)
1mS
SRC_Stop# PWRDWN#
DIF (Free Running) DIF# (Free Running)
DIF (Stoppable) DIF# (Stoppable)
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Integrated Circuit Systems, Inc.
ICS9DB108
N
c
SYMBOL
L
E1 INDEX AREA
E
12 h x 45 D
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
Ordering Information
ICS9DB108yFLFT
Example:
ICS XXXX y F LF T
Designation for tape and reel packaging Lead Free (optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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Integrated Circuit Systems, Inc.
ICS9DB108
N
c
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil)
L
(20 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .011 .0035 .008 SEE VARIATIONS 0.319 BASIC .236 .244 0.020 BASIC .018 .030 SEE VARIATIONS 0 8 -.004
SYMBOL A A1 A2 b c D E E1 e L N a aaa
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20 0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 -0.10
-Ce
b SEATING PLANE
VARIATIONS N 48 D mm. MIN 12.40 MAX 12.60 MIN .488 D (inch) MAX .496
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS9DB108yGLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging Lead Free (optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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